The invention relates to a semiconductor device of pnpn structure used for power devices and so on, and more particularly a semiconductor device of double gate type with two gate electrodes.
One of the most important key technologies to solve problems, such as high performance, miniaturization and low-cost in power electronics, is to lower the loss of power devices, and the development of devices with low on-state voltage and short turn-off time is actively developing in many fields. For instance, bipolar transistors with high performance, high voltage and large current have been achieved, and intelligent modules containing therein various protection functions have been made. Moreover, IGBT (conductivity modulation transistor, insulated gate bipolar transistor) of high-speed response has been made.
These power devices are applied to miniaturized electrical apparatus to which electricity is supplied from a battery to be able to easily carry, inverters, electric vehicles which are being examined from the view point of environmental protection, etc. and bear the role of electric power conservation. And, in order to respond to demand for electric power increasing more and more in recent years, the power conservation and low loss in power devices are further required to these power semiconductor devices.
For instance, EST (emitter switched thyristor) to reduce on-state voltage by thyristor structure and to make high speed and low driving power by MOS gate device has been developed. This EST is a device which has a structure and an equivalent circuit shown in FIGS. 8 and 9.
This EST comprises a collector layer 2 of a p.sup.+ type semiconductor substrate (anode layer of a thyristor) with which a collector electrode 1 (anode electrode of the thyristor) is formed; an n.sup.+ type buffer layer 3 formed on the collector layer 2; an n.sup.- type base layer 4 (drift layer) formed on the buffer layer 3; a p type base region 5 in the form of well and being formed in the main face side of the n.sup.- type base layer 4; an n.sup.+ type emitter region 6 (cathode region of the thyristor) formed in the main face side of the p type base region 5; an n.sup.+ type source region 7 formed in the main face side of the p type base region 5 and isolated from the p.sup.+ type emitter region 6; an emitter electrode 8 (cathode electrode of the thyristor) which conductively contacts both main face of the p type base region 5 and the n.sup.+ type source region 7; a first gate electrode 9 which uses the p type base region 5 as a back gate (channel region) and is formed to cover the n.sup.+ type emitter region 6 and the n.sup.- type base layer 4 through a gate insulation film 9a; and a second gate electrode 11 which uses the p type base region 5 as a back gate (channel region) and is formed to cover the n.sup.+ type source region 7 and the n.sup.+ type emitter region 6 through a gate insulation film 10, the second gate electrode conductively contacting the first electrode 9.
The first gate electrode 9, the emitter region 6, a channel part M1 in the p type base region 5 and the n.sup.- type base layer 4 form a first MOSFET 12 for ON. The second gate electrode 11, the n.sup.+ type source region 7, a channel part M2 in the p type base region 5 and the emitter region 6 form a second MOSFET 13 (emitter switch) for short-circuit. The first MOSFET 12 and the second MOSFET 13 are insulated gate field effect transistors of n channel type.
Moreover, the p.sup.+ type collector layer 2, the n.sup.+ type buffer layer 3, the n.sup.- type base layer 4 and the p type base region 5 form a pnp type bipolar transistor Q.sub.pnp. The n.sup.- type base layer 4, the p type base region 5 and the n.sup.+ type emitter region 6 form an npn type bipolar transistor Q.sub.npn. Besides, a base resistance R.sub.B (diffused resistor) exists as a short circuit resistance because the emitter electrode 8 contacts the p type base region 5. The above-mentioned semiconductor structures are symmetric with respect to the axis at the center of the emitter electrode 8, and the structure shown in FIG. 8 shows only the right half of the device.
When a high voltage is applied to the gate electrodes 9, 11, at first, the MOSFETs 12 and 13 conduct, so that majority carriers (electrons) are injected into the n.sup.- type base layer 4 through the emitter electrode 8, the source region 7, the channel part M2, the emitter region 6 and the channel part M1. At the same time, minority carriers (holes) flow into the n.sup.- type base layer 4 through the collector electrode 1, the collector region 2 and the buffer layer 3, so that the conductivity of the n.sup.- type base layer 4 is modulated. Since the transistor Q.sub.pnp is turned ON with this, the transistor Q.sub.npn is turned on, and the thyristor pnpn turns on.
As shown in FIG. 10(a), in the on-state of this thyristor, an electron current (solid line arrow) flows through the channel part M1, and simultaneously the hole current (dashed line arrow) and electron current flow through the junction of the n.sup.+ type base region 5 and the p type emitter region 6, wherein the junction between the base region 5 and the emitter region 6 is forward biased.
Next, when zero or negative voltage is applied to the gate electrodes 9, 11, the MOSFETs 12 and 13 are cut off, and the injecting of the majority carriers to the n.sup.- type base layer 4 stops and the conduction between the emitter region 6 and the source region 7 is cut off. Therefore, the transistor Q.sub.npn becomes off-state, so that the transistor Q.sub.pnp turns off and the thyristor pnpn is also turned off. The n.sup.+ type buffer layer 3 is formed to shorten the turn off time by restraining the injecting efficiency of the holes (minority carriers) from the collector layer 2 to the base layer 4 of n.sup.- type.
When the thyristor operates, a current flows from the n.sup.- type base layer 4 into the n.sup.+ type emitter region 6 through the p type base region 5, wherein the p-n junction of the p type base region 5 and the n.sup.+ type emitter region 6 is in the state of forward bias and the electric potential barrier of the p-n junction is lost. Thus, as shown in FIG. 10(b), if the conduction between the emitter region 6 and the source region 7 is cut off by turning off the MOSFET 13 at the initial stage of the turn-off operation, the p-n junction of the p type base region 5 and the n.sup.+ type emitter region 6 is in the state of forward bias due to a voltage drop across a short circuit resistance R.sub.B. This potential barrier does not recover easily, wherein the holes flow for a while through the junction and accumulate into the emitter region 6.
To shorten the turn-off time due to the recovery lag of the potential barrier according to the p-n junction of the p type base region 5 and the n.sup.+ type emitter region 6 at the turn-off of the thyristor, the second MOSFET 13 for short circuit switches off between the source region 7 and the emitter region 6, that is, internally disconnects between the emitter region 6 as a substantial cathode region and the emitter electrode 8 as a substantial cathode electrode. In the turn off operation, since the secondary current flowing through the base resistance R.sub.B remains only at the first stage, the turn-off time can be shortened.
However, since a coupling capacity Cg.sub.d is parasited (parasitic capacity) between the gate electrode 11 and the emitter region 6 as a drain region of the second MOSFET 13, if the recovery of the potential barrier due to the p-n junction of the p type base region 5 and the n.sup.+ type emitter region 6 is late, the voltage rises since the positive holes accumulate in the n.sup.+ type emitter region 6, and in response to this, the gate potential rises. Thus, breakdown of the gate insulation film 10 and repetition of ON of the MOSFET 13 happen easily. Therefore, though it is necessary to reduce the current flowing into the n.sup.+ type emitter region 6 at turn off, if the current is reduced, it comes to reduction of controllable turn-off current and prolongation of the turn-off time, so that there is a limit as a power device. On the other hand, it may be considered to raise breakdown voltage by thickening the gate insulation film 10, but the on-state voltage rises.
Thus, the present invention has been made with reference to the above problems, and the object of the present invention is to provide a semiconductor device which has a low on-voltage and can obtain a large controllable turn-off current by restraining the current flow into the emitter region by changing current path by IGBT operation once at turn-off.